The ever-increasing use of mobile communications is driving improvements in radio frequency (RF) communications. In particular, this expanding market is demanding lower power consumption and increased performance. One possible solution that has found many applications is bipolar complementary metal-oxide semiconductor (BiCMOS) technology. See, e.g., Chyan et al., “A 50 GHz 0.25 μm . . . BiCMOS Technology for Low-Power Wireless-Communication VLSI's,” BCTM, 1998, page 128.
However, many BiCMOS circuit designs are limited in terms of speed, power consumption, and noise, because only high performance vertical NPN transistors are currently available. Low performance lateral PNP transistors are available, which have a cutoff threshold (fT) of less than 1 GHz and cannot compliment the high-speed NPN bipolar devices for forming push-pull circuits. There is therefore a continuing need in the art for high performance PNP transistors. See, e.g., D. M. Monticelli, “The Future of Complementary Bipolar,” BCTM, 2004, page 21.
Further, it is expensive to integrate the PNP transistors into a conventional BiCMOS process that is designed to form only complementary metal-oxide-semiconductor (CMOS) devices and NPN bipolar devices. Additional processing steps are typically required for forming PNP transistors, which result in prolonged processing time and increased manufacturing costs. Therefore, a need also exists for a method for integrating PNP transistor processing steps into a conventional BiCMOS process, with few or no additional processing steps.